The present invention relates to an apparatus for sampling a fast rate repeated waveform with a slower rate clock to convert it into a low rate waveform for purpose of observation, measurement and analysis (such apparatus will be hereafter referred to as xe2x80x9csampling digitizerxe2x80x9d), such a method and a semiconductor integrated circuit testing equipment provided with a sampling digitizer.
As is well known in the art, a sampling digitizer, comprises a sampling head 11, a clock generator 12, an apparatus (hereafter referred to as xe2x80x9cdigitizer sectionxe2x80x9d) 13 which observes, measures and/or analyzes a signal waveform, and a trigger circuit 14, as illustrated in FIG. 1. The sampling digitizer converts a high rate repeated signal (waveform) HRS input to the sampling head 11 (usually formed by a circuit including a diode bridge) into a low rate repeated signal (waveform) by an equivalent sampling technique to be described later, and performs an observation, measurement and analysis of the input waveform of the high rate repeated signal HRS by observing, measuring and analyzing the waveform of the low rate repeated signal.
The equivalent sampling technique is illustrated in FIG. 2A for a high rate repeated signal HRS having a period T and input to the sampling head 11, as an example. In this instance, the clocking generator 12 generates a clock signal CLK1 and supplies it to the sampling head 11 at a given sampling rate (period) T1 equal to (nT+xcex94t) such that sample timings t1, t2, t2, . . . for the repeated signal HRS be sequentially offset in their phases within the period T by a minimal time interval xcex94t which corresponds to a constant phase (in the example shown, the phase of the sample timings is sequentially lagging by xcex94t). The given minimal interval xcex94t by which the phase of the sample timing is sequentially offset in the period T is referred to in the art as xe2x80x9cequivalent sampling intervalxe2x80x9d. When the frequency of a clock signal CLK having a period equal to a time interval nT obtained by subtracting the equivalent sampling interval from the period T1 is denoted by F, n is equal to the quotient of dividing the frequency of the high rate repeated signal HRS by the frequency F of the clock signal CLK. Usually, the frequency F of the clock signal CLK is chosen relative to the frequency of the high rate repeated signal HRS so that the quotient n is an integer.
As a consequence of this, the sampling head 11 delivers a low rate data signal OUT1 at the sampling rate T1. As shown in FIG. 2C, the low rate data signal OUT1 appears as converted into a waveform data train a, b, c, . . . in which the amplitude level changes stepwise in alignment with sample timings t1, t2, t3, . . . Waveform data train a, b, c, . . . is downloaded into the digitizer section 13, and when it is superimposed every period nT, the waveform data a, b, c, . . . are plotted at a time interval of the equivalent sampling interval xcex94t. Accordingly, as shown in FIG. 2D, there is obtained a low rate repeated signal LRS1 having a period T3 which is equal to the sampling rate T1 multiplied by the number of samples per period T of the high rate repeated signal HRS. It follows that the waveform of the low rate repeated signal LRS1 is substantially identical with the waveform of the high rate repeated signal HRS.
It is to be noted that in order to facilitate the understanding of the equivalent sampling technique, the waveform of the high rate repeated signal HRS is shown enlarged and the equivalent sampling interval xcex94t is shown lengthened in FIG. 2. Thus, in FIG. 2, n=3 and the sampling rate T1=3T+xcex94t. However, the high rate repeated signal HRS generally has a frequency which is much greater than the frequency F of the clock signal CLK, and accordingly, n assumes a significantly higher value.
Describing this in terms of specific figures, the high rate repeated signal HRS may have a frequency of 1 GHz (or its period is 1 ns) while the internal clock signal CLK of the clock generator 12 may have a frequency F of 100 kHz. Assuming in this instance that the number of samples per period T (1 ns) of the high rate repeated signal HRS is equal to 100 (thus acquiring 100 data items per period T while sequentially delaying the phase of the sample timing by the equivalent sampling interval xcex94t), it follows that adjacent two sample points are spaced apart by 1 ns/100=10 ps, which is the equivalent sampling interval xcex94t. Consequently, the clock generator 12 generates and delivers to the sampling head 11 the clock signal CLK1 at the sampling rate T1=1 nsxc3x97(1 GHz/100 kHz)+10 ps=10 xcexcs+10 ps. The sampling head 11 delivers the waveform data train a, b, c, . . . in which the amplitude level changes stepwise at sample timings t1, t2, t3, . . . at the sampling rate T1=10 xcexcs+10 ps. Such waveform data is downloaded into the digitizer section 13. When downloaded waveform data is synthesized at a time interval between the sample timings or the equivalent sampling interval of 10 ps (or xcex94t), there is obtained the low rate repeated signal LRS1 having a period T3 corresponding to (10 xcexcs+10 ps)xc3x97100 as shown in FIG. 2D.
The trigger circuit 14 has the function of establishing a start point of observation, measurement and/or analysis of the waveform of the high rate repeated signal HRS. Specifically, information relating to a start point of observation, measurement and/or analysis of the waveform such as a level, a rising edge, a falling edge or the like (hereafter referred to as xe2x80x9ctrigger informationxe2x80x9d) is preset in the trigger circuit 14. When trigger information contained in the data signal OUT1 (waveform data train a, b, c, . . .) which is fed from the sampling head 11 to the trigger circuit 14 matches the trigger information which is preset in the trigger circuit 14, the latter produces a trigger signal TR, which is applied to the digitizer section 13. The digitizer section 13 initiates downloading the waveform data train from the time the trigger signal is applied thereto. Thus from the time (hereafter referred to as xe2x80x9ctrigger pointxe2x80x9d) the trigger circuit 14 produces the trigger signal TR, the observation, measurement, analysis and the like of the waveform of the high rate repeated signal HRS is initiated using the low rate repeated signal LRS1. Instead of directly feeding the sampled output of the sampling head 11 to the digitizer section 13 and the trigger circuit 14, the output may be converted into digital values by an A/D converter, not shown, before being fed to the digitizer section 13 and the trigger circuit 14. Thus, it should be understood that the output data signal from the sampling head 11 may comprise the original sampled signal or the converted digital signal as the case may be in the description to follow.
As described, with a conventional sampling digitizer, because the start point of the observation, measurement, analysis and the like is defined by the trigger point, the observation, measurement, analysis and the like of the waveform is limited to a portion thereof which occurs after the trigger point as a matter of course. If the trigger point is represented by a point a in the waveform shown in FIG. 2D, for example, no observation, measurement, analysis and the like of a waveform portion which precedes point a in time (or located to the left thereof as viewed in FIG. 2D) is allowed.
A waveform region of a high rate repeated signal HRS for which an observation, measurement, and/or analysis is desired is generally a fraction of one period T of the high rate repeated signal HRS, which is frequently a rising edge region of the waveform as an example. As described above, because the trigger point defines the start point of the observation, measurement, analysis and the like of the waveform, supposing that point a in the waveform of FIG. 2A defines the trigger point, the trigger circuit 14 does not generate the trigger signal TR until the waveform data a shown in FIG. 2C is delivered from the sampling head 11 and is input to the trigger circuit 14, thus preventing the observation, measurement, analysis and the like of the waveform portion which occurs at and subsequent to the trigger point, as desired.
An N-channel sampling digitizer as shown in FIG. 3 (where N is an integer equal to or greater than 2) is also used in the prior art. It comprises a plurality of sampling heads 11 and a plurality of digitizer sections 13, each operating according to the described equivalent sampling technique to convert a high rate repeated signal into a low rate repeated signal, thus enabling a simultaneous observation, measurement, and analysis and the like of the converted signal waveforms by the plurality of digitizer sections.
In the example shown in FIG. 3, a plurality of high rate repeated signals HRS1, HRS2, . . . HRSN of a substantially equal phase are input to associated sampling heads 11-1, 11-2, . . . 11-N, respectively, which are simultaneously fed with a clock signal CLK1 from a common clock generator 12 at a given sampling rate, which may be the sampling rate T1 shown in FIG. 2B, for example. In response thereto, the sampling heads 11-1 to 11-N deliver low rate data signals OUT1, OUT2, . . . OUTN, respectively, each comprising a waveform data train as converted in which the amplitude level changes stepwise at the sample timings.
By way of example, when high rate repeated signals HRS1, HRS2, . . . , HRSN which rise substantially simultaneously are input to a plurality of sampling heads 11-1, 11-2, . . . , 11-N, and a common clock generator 12 generates a clock signal CLK1 at a constant sampling rate T1 such that the phase of sample timings for the repeated signals HRS1 to HSN are sequentially offset by an equivalent sampling interval xcex94t (for example, the phase of the sample timing is sequentially delayed by xcex94t), the sampling heads 11-1 to 11-N deliver low rate data signals OUT1 to OUTN in which the amplitude level changes stepwise at the sample timings in the similar manner as shown in FIG. 2C for the low rate data signal OUT1 at the sampling rate T1.
Only one trigger circuit 14 is provided for the plurality of digitizer sections 13-1, 13-2, . . . , 13-N in common, and data signal OUT from any one of the plurality of sampling heads 11-1 to 11-N, which is data signal OUTN from the N-th sampling head 11-N in this example, is fed as an input signal to the trigger circuit 14. Obviously, data signal from any other sampling head may be fed as an input signal to the trigger circuit 14.
In response to a trigger signal TR applied from the common trigger circuit 14, the plurality of digitizer sections 13-1, 13-2, . . . , 13-N initiate downloading the data signals OUT1, OUT2, . . . , OUTN fed from the associated sampling heads 11-1, 11-2, . . . , 11-N. Assuming that the trigger point represents a rising point L of a waveform, the digitizer sections 13-1 to 13-N download a substantially similar waveform data which begins with the trigger point L since the plurality of sampling heads 11-1 to 11-N deliver substantially similar waveform data. Accordingly, an observation, measurement, analysis and the like of the waveform is only allowed after the trigger point of the high rate repeated signals HRS1 to HRSN even with the N channel sampling digitizers shown in FIG. 3.
The sampling digitizer mentioned above is also used in a semiconductor integrated circuit testing equipment (IC tester) which tests a semiconductor integrated circuit (subsequently referred to as IC). Specifically, a sampling digitizer is used in testing whether or not an IC under test can positively respond to a given high rate signal or determining to which high rate signal it can respond by applying a test pattern signal to the IC under test at a high rate, and observing and measuring the waveform of a low rate signal which is converted from a response signal delivered at a high rate from the IC under test.
As is well recognized, an IC having a logic circuit as its main is referred to as a logic IC while an IC having a memory as its main is referred to as a memory IC. An IC having a mixture of a logic section and a memory section in one chip is referred to as a system LSI, a system on chip (SOC) or the like. FIG. 4 shows a schematic arrangement of an IC testing equipment (hereafter referred to as IC tester) which is commonly used in the art. The IC tester shown comprises an IC tester body 100 and a test head 200. In the example shown, the IC tester body 100 comprises a controller 101, a timing generator 102, a pattern generator 103, a waveform formatter 104, a driver 105, a comparator 106, a logic comparator 107, a defect analysis memory 108 and a voltage generator 109.
The test head 200 is constructed separately from the IC tester body 100, and is usually provided with a given number of IC sockets (not shown) which are mounted on the top thereof. The test head 200 internally contains a printed substrate which is referred to as a pin card in the art, and usually a circuit of the IC tester body 100 including the driver 105 and the comparator 106 is mounted on the pin card. The pin card is provided for each I/O pin (input/output terminal) of an IC under test 300. The test head 200 is generally mounted on a test section of an IC conveying and processing unit which is referred to as a handler in the art, and is electrically connected to the IC tester body 100 through signal transmission means such as a cable, an optical fiber or the like.
The IC under test 300 is mounted on the IC socket of the test head 200. A test pattern signal form the IC tester body 100 is applied to the IC under test, which is commonly referred to as DUT, 300 while a response signal from the IC under test 300 is supplied to the IC tester body 100 through the IC socket, thus performing a test and a measurement of the IC under test 300.
The controller 101 comprises a computer system in which a test program prepared by a user or programmer is previously stored, and the entire IC tester is controlled in accordance with the test program. The controller 101 is connected to the timing generator 102, the pattern generator 103, the waveform formatter 104, the logic comparator 107, the defect analysis memory 108 and the voltage generator 109 through a tester bus 111, and the timing generator 102, the pattern generator 103, the waveform formatter 104, the logic comparator 107, the defect analysis memory 108 and the voltage generator 109 operate as terminals to carry out a testing of the IC under test 300 in accordance with control instructions delivered from the controller 101.
A test, for example, a functional test, of the IC under test 300 takes place as follows:
The pattern generator 103 is previously loaded with a pattern generation sequence which is described in the test program which is stored in the controller 101 before starting a test, and in response to a test start instruction from the controller 101, the pattern generator 103 delivers a test pattern data which is to be applied to the IC under test 300 in accordance with the stored pattern generation sequence. ALPG (algorithmic pattern generator) is generally used for the pattern generator 103. ALPG refers to a pattern generator which includes internal registers having arithmetic capabilities to generate a test pattern to be applied to a semiconductor device by arithmetic operations.
Timing data which is delivered every test period and which is described in the test program stored in the controller 101 is previously loaded in the timing generator 102 before starting a test, and the timing generator 102 delivers a clock pulse for each test period in accordance with the stored timing data. Such clock pulse is applied to the waveform formatter 104, the logic comparator 107 and the like.
The waveform formatter 104 defines the timing of a rising edge and a falling edge of a logic waveform on the basis of the test pattern data delivered from the pattern generator 103 and the clock pulse delivered by the timing generator 102 to form a test pattern signal having an actual waveform which varies between an H logic (or logic xe2x80x9c1xe2x80x9d) and an L logic (or logic xe2x80x9c0xe2x80x9d), which is in turn applied to the IC under test 300 through the driver 105.
The driver 105 controls the amplitude of the test pattern signal delivered from the waveform formatter 104 to a desired value (or to a voltage VIH corresponding to the H logic or logic xe2x80x9c1 xe2x80x9d and a voltage VIL corresponding to the L logic or logic xe2x80x9c0xe2x80x9d) before applying it to the IC socket of the test head 200, thus driving the IC under test 300.
The comparator 106 determines whether or not the logic value of a response signal delivered form the IC under test 300 has a normal logic value, thus, whether a voltage corresponding to the H logic has a value equal to or greater than a given voltage VOH and a voltage corresponding to the L logic has a value equal to or less than a voltage VOL.
When a result of decision is acceptable, an output signal from the comparator 106 representing such result of decision is input to the logic comparator 107 where it is compared against an expected value pattern data which is delivered from the pattern generator 103, thus determining whether or not the IC under test 300 has delivered a normal response signal. A result of comparison by the logic comparator 107 is downloaded into the defect analysis memory 108. In the event a defect has occurred, the test pattern address for which the defect is found, an output logic data on a defective pin or pins on the IC under test 300 and a corresponding expected value pattern data are stored in the defect analysis memory 108, and used in the evaluation of the LSI subsequent to the completion of the test.
The voltage generator 109 generates amplitude voltages VIH and VIL which are to be applied to the driver 105 and compared voltages VOH and VOL which are to be applied to the comparator 106 in accordance with preset values delivered from the controller 101. In this manner, the driver 105 generate drive signals having amplitude values which conform to the specification of the IC under test 300, and the comparator 106 is enabled to determine whether the response signal from the IC under test 300 have logic values for the voltages which conform to the specification of the IC under test 300.
The described sampling digitizer is mounted on the pin card which is contained within the test head 200 in order to observe, measure and/or analyze the waveform of a response signal which is rapidly read out from the IC under test 300, for example. Thus, the test pattern signal is applied at a high rate to the IC under test 300, and the waveform of response signals which are delivered at high rate from respective pins of the IC under test is observed, measured and/or analyzed using the sampling digitizer mentioned above. The observation, the measurement, the analysis and the like of the waveform allows a decision to be rendered whether the IC under test 300 is defective or not. As a result of such test, the operating speed of the IC under test can be classified into categories, for example, and it is also possible to test to which high rate signal the IC under test can positively respond.
As mentioned previously, with a conventional sampling digitizer, the observation, the measurement and/or analysis of the waveform of a high rate repeated signal which is input to a sampling head is possible only after the trigger point. However, it is often desired that a waveform which immediately precedes the trigger point or a waveform across the trigger point be emphatically observed, measured and/or analyzed.
If it is desired to download waveform data which precedes the trigger point into the digitizer section 13 or 13-1 to 13-N in the arrangement of the sampling digitizers shown in FIGS. 1 and 3, it is necessary that the digitizer section 13 or 13-1 to 13-N be operated continuously, and the downloading of waveform data must be interrupted at the trigger point to allow the downloaded data to be read out. Assuming that the waveform data begins to be downloaded immediately after the trigger point, this requires a time interval corresponding to one period (T3) until the next trigger point is reached and the provision of a memory which is capable of storing waveform data for about one period (T3). As a consequence, when it is desired to observe, measure and/or analyze emphatically a waveform region which precedes the trigger point, for example, a waveform region which immediately precedes the trigger point, a time interval corresponding to about one period at most must be provided in order to download the waveform data, and simultaneously there must be provided a memory having a capacity capable of storing the waveform data for about one period. In other words, it has been impossible to download a required waveform region in a reduced length of time.
Alternatively, in order to download a waveform data across the trigger point into the digitizer section 13 or 13-1 to 13-N, it is necessary that the digitizer section 13 or 13-1 to 13-N be operated continuously, and the downloading of the waveform data be interrupted at a point past the trigger point where a given number of samples of waveform data have been acquired. However, it is again necessary to take into consideration that the downloading of waveform data may be started immediately after the trigger point has been passed, and this again requires a time interval corresponding to about one period (T3) until the next trigger point is reached, and the provision of a memory capable of storing the waveform data for at least one period (T3). Thus, the difficulties that a time interval corresponding to one period or greater is necessary and that a memory having a capacity capable of storing the waveform data for at least one period must be provided remain unchanged also when it is desired that a waveform region across the trigger point be emphatically observed, measured and/or analyzed. Again, it has been impossible to download a required waveform region in a reduced length of time.
When a high rate repeated signal HRS is input to the sampling head 11, and when a waveform region which is desired to be observed, measured and/or analyzed or which is desired to be downloaded into the digitizer section 13 represents a rising edge region, it is to be noted that such rising edge region is a very small portion of one period T of the high rate repeated signal HRS, which may be on the order of one-tenth of the period, for example. FIGS. 5A and 5B show the waveform of the high rate repeated signal HRS shown in FIG. 2A and the waveform of the low rate repeated signal LRS1 shown in FIG. 2B to an enlarged scale. If the time interval for the rising edge region LE of the high rate repeated signal HRS having the period T is equal to about one-tenth the period T, it follows that as considered with respect to the low rate repeated signal LRS1 shown in FIG. 5B which is synthesized and reproduced with the equivalent sampling interval xcex94t (for example, 10 ps), there is a waiting time WT equal to nearly {fraction (9/10)} the period T3 at most until the beginning (the trigger point Tr) of the rising edge region LE, which is a waveform region to be observed, measured and/or analyzed is reached. It will be noted that this waiting time WT is very long (nearly nine times) in comparison to the time necessary to download the required waveform region LE into the digitizer section 13.
Illustrating this in terms of specific figures, it may be assumed that the rising edge region LE has a time fraction of {fraction (1/10)}, for example, with respect to the period T of the high rate repeated signal HRS, and that 16xc3x97103 items of data be downloaded into the digitizer section 13 during the time interval for the rising edge region LE. If a sampling rate of 1 xcexcs is used, a time length of 16xc3x97103xc3x9710xe2x88x926(xcexcs)=16 ns is required to download the data in the rising edge region LE. Accordingly, a maximum waiting time WT will be 16 nsxc3x979=144 ns, meaning that a waiting time which is nine times, at maximum, the time interval necessary to download the data for the rising edge region LE is required until the trigger point Tr is reached. Thus, this represents a disadvantage that the efficiency of using the arrangement is greatly degraded.
It is an object of the present invention to provide a sampling digitizer and an associated method which allow a required waveform region to be downloaded in a reduced length of time.
It is another object of the invention to provide a sampling digitizer and an associated method which allow an observation, measurement and/or analysis of a waveform region which precedes a trigger point to be made in a reduced length of time without the need to increase a memory capacity.
It is a further object of the invention to provide a sampling digitizer and an associated method which allow an emphatic observation, measurement and/or analysis of a waveform region across a trigger point to be made in a reduced length of time without the need to increase a memory capacity.
It is an additional object of the invention to provide a sampling digitizer and an associated method for reducing a waiting time until a trigger point is reached and for improving the efficiency of using an arrangement.
It is still another object of the present invention to provide a semiconductor integrated circuit testing equipment which allows a testing time for a semiconductor integrated circuit (IC) to be reduced while enabling a testing with a higher accuracy.
According to a first aspect of the present invention, there is provided a sampling digitizer comprising clock generator means for generating a clock signal, a sampler for sampling an input high rate repeated signal with a clock signal supplied from the clock generator means to convert it into a low rate data signal, a signal waveform observing, measuring or analyzing unit to which the data signal from the sampler is supplied, trigger means to which the data signal from the sampler is supplied for generating a trigger signal when the data signal contains trigger information, delay means for delaying the clock signal supplied from the clock generator means to the sampler, and switching means for switching between the clock signal which is caused to pass through the delay means and the clock signal which is directly supplied from the clock generator means, to be supplied to the sampler. The low rate data signal may comprise a sampled output itself or a digital counterpart of the sampled output. This applies also in the description to follow.
In a preferred embodiment, the switching means carries out a switching between the clock signals in response to the trigger signal from the trigger means. Before the trigger signal is applied, the clock signal which has been caused to pass through the delay means is supplied to the sampler while after the trigger signal from the trigger circuit is applied, the clock signal which is directly delivered from the clock generator means is supplied to the sampler.
The clock signal generated by the clock generator means has a sampling rate corresponding to a period which is defined as a sum of a quotient of the frequency of the high rate repeated signal divided by the frequency of the internal clock signal generated by the clock generator means, multiplied by a time interval corresponding to one period of the high rate repeated signal and an equivalent sampling interval which is equal to the time corresponding to one period of the high rate repeated signal divided by the number of samples per period of the high rate repeated signal.
According to a second aspect of the present invention, there is provided a sampling digitizer having a plurality of channels, each channel including a sampler for sampling an input high rate repeated signal at a given sampling rate to convert it into a low rate data signal and a signal waveform observing, measuring or analyzing unit to which the data signal from the sampler is supplied. In accordance with the present invention, the sampling digitizer further comprises a single clock generator which is common to the plurality of channels for generating a clock signal at a given sampling rate, single trigger means which is common to the plurality of channels to which data signal from the sampler of a specific one of the plurality of channels is supplied as an input signal for generating a trigger signal to be supplied to the signal waveform observing, measuring or analyzing unit of each channel when the data signal contains trigger information, and delay means for causing the clock signal which is supplied from the clock generator means to the sampler of that channel which supplies the data signal to the trigger means to be delayed.
According to a third aspect of the present invention, a sampling digitizer comprises clock generator means for generating a clock signal, a sampler for sampling an input high rate repeated signal with the clock signal supplied from the clock generator means to convert it into a low rate data signal, a signal waveform observing, measuring or analyzing unit to which the data signal from the sampler is supplied, trigger means to which the data signal from the sampler is supplied for generating a trigger signal when the data signal contains trigger information, and means for supplying the trigger signal generated by the trigger means to the clock generator means to increase the frequency of the clock signal which is generated by the clock generator means.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit testing equipment in which a test pattern signal is applied to a semiconductor integrated circuit under test, a response signal which is read out from the semiconductor integrated circuit under test is logically compared, and the semiconductor integrated circuit under test is determined to be acceptable or defective on the basis of a result of the comparison, and comprising a sampling digitizer according to one of the first and the second aspect of the present invention.
In a preferred embodiment, the sampling digitizer is mounted on a pin card which is contained in a test head of the semiconductor integrated circuit testing equipment. Other aspects of the present invention will be described with reference to the embodiments.